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v3.1
40MX and 42MX Automotive FPGA Families
Features High Capacity
* * * * * Single-Chip ASIC Alternative for Automotive Applications 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 202 User-Programmable I/O Pins
Ease of Integration
* * * * * Up to 100% Resource Utilization and 100% Pin Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Low Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device Capacity System Gates SRAM Bits Logic Modules Sequential Combinatorial Decode SRAM Modules (64x4 or 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks Maximum User I/Os Boundary Scan Test (BST) Packages (by pin count) PLCC PQFP VQFP TQFP A40MX02 3,000 - - 295 - - - 147 1 57 - 68 100 80 - A40MX04 6,000 - - 547 - - - 273 1 69 - 84 100 80 - A42MX09 14,000 - 348 336 - - 348 516 2 104 - 84 100, 160 100 176 A42MX16 24,000 - 624 608 - - 624 928 2 140 - - 208 100 176 A42MX24 36,000 - 954 912 24 - 954 1,410 2 176 Yes - 160, 208 - 176 A42MX36 54,000 2,560 1,230 1,184 24 10 1,230 1,822 6 202 Yes - 208, 240 - -
Note: While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial, industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the 40MX and 42MX Family FPGAs datasheet for more details.
May 2006 (c) 2006 Actel Corporation
i See the Actel website (www.actel.com) for the latest version of this datasheet.
40MX and 42MX Automotive FPGA Families
Ordering Information
A42MX16 _ PQ 208 A
Application (Temperature Range) A = Automotive (-40 to +125C) Package Lead Count Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin Quad Flat Pack (1.4 mm) VQ = Very Thin Quad Flat Pack (1.0 mm) Speed Grade (Blank for Standard) Part Number A40MX02 = 3,000 System Gates A40MX04 = 6,000 System Gates A42MX09 = 14,000 System Gates A42MX16 = 24,000 System Gates A42MX24 = 36,000 System Gates A42MX36 = 54,000 System Gates Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing options available.
Plastic Device Resources
Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 68-Pin 57 - - - - - PLCC 84-Pin - 69 72 - - - PQFP 100-Pin 57 69 83 - - - PQFP 160-Pin - - 101 - 125 - User I/Os PQFP 208-Pin - - - 140 176 176 PQFP 240-Pin - - - - - 202 VQFP 80-Pin 57 69 - - - - VQFP 100-Pin - - 83 83 - - TQFP 176-Pin - - 104 140 150 -
Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack
Speed Grade and Temperature Grade Matrix
Std A
Note: Refer to the 40MX and 42MX Family FPGAs datasheet for details on commercial-, industrial- and military-grade MX offerings.
Contact your local Actel representative for device availability.
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v3.1
40MX and 42MX Automotive FPGA Families
Table of Contents
40MX and 42MX Automotive FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-25 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Package Pin Assignments
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 100-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 160-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 240-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
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40MX and 42MX Automotive FPGA Families
40MX and 42MX Automotive FPGA Families
General Description
Actels' automotive-grade MX families provide a highperformance, single-chip solution for shortening the system design and development cycle, offering a costeffective alternative to ASICs for in-cabin telematics and automobile interconnect applications. The 40MX and 42MX devices are excellent choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs. The MX device architecture is based on Actel's patented antifuse technology implemented in a 0.45m triplemetal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX devices are live on power-up and have one-fifth the standby power consumption of comparable FPGAs. Actel's MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades. The automotive-grade 42MX24 and 42MX36 include system-level features such as IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can efficiently address applications requiring wide datapath manipulation. flops can be constructed from logic modules whenever required in the application. The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and decode (D-modules). Figure 1-2 illustrates the combinatorial logic module. The S-module, shown in Figure 1-3 on page 1-2, implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. The S-module register can be bypassed so that it implements purely combinatorial logic. A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD architectures (Figure 1-4 on page 1-2). The Dmodule allows A42MX24 and A42MX36 devices to perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic.
MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within these families are composed of logic modules, I/O modules, routing resources and clock networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain widedecode modules.
Figure 1-1 * 40MX Logic Module
A0 B0
D00 D01 D10 D11 A1 B1 S1 Y
Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1-1). The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array; latches and flipv3.1
S0
Figure 1-2 * 42MX C-Module Implementation
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40MX and 42MX Automotive FPGA Families
D00 D01 D10 D11 S1 S0 Y D CLR Q OUT
D00 D01 D10 D11 S1 S0 Y
D GATE
Q
OUT
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 7-Input Function Plus Latch
D00 D0 Y D1 S D GATE CLR Q OUT D01 D10 D11 S1 S0 Y OUT
Up to 4-Input Function Plus Latch with Clear
Up to 8-Input Function (Same as C-Module)
Figure 1-3 * 42MX S-Module Implementation
7 Inputs Hard-Wire to I/O Programmable Inverter Feedback to Array
Figure 1-4 * A42MX24 and A42MX36 D-Module Implementation
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules, which are arranged in 256-bit blocks and can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of userdefinable width and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5 on page 1-3. The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]) and eight outputs (RD[7:0]), which are connected to segmented vertical routing tracks. The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO and LIFO queues. The ACTgen Macro Builder within Actel's Designer software provides capability to quickly design memory functions with the SRAM blocks.
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40MX and 42MX Automotive FPGA Families
WD[7:0]
Latches [7:0]
WRAD[5:0]
[5:0] Latches
Write Port Logic
SRAM Module 32 x 8 or 64 x 4 (256 Bits)
[5:0] Read Port Logic
Latches Read Logic
RDAD[5:0]
REN RCLK
MODE BLKEN WEN WCLK
Write Logic
RD[7:0]
Routing Tracks
Figure 1-5 * A42MX36 Dual-Port SRAM Block
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be continuous or split into segments. Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses.
above and two below), except near the top and bottom of the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 1-6.
Segmented Horizontal Routing
Logic Modules
Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located in between the rows of modules. Any segment that spans more than one-third of the row length is considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-dedicated tracks are used for signal nets.
Antifuses
Vertical Routing Tracks
Figure 1-6 * MX Routing Structure
Antifuse Structures
An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. There are no pre-existing connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For instance, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks: input, output, and long. Long tracks span the column length of the module, and can be divided into multiple segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two
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40MX and 42MX Automotive FPGA Families
Clock Networks
The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK network by being routed through the CLKBUF buffer. In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal from any of the following (Figure 1-7): * * * Externally from the CLKA pad, using CLKBUF buffer Externally from the CLKB pad, using CLKBUF buffer Internally from the CLKINTA input, using CLKINT buffer
CLKB CLKA From Pads
*
Internally from the CLKINTB input, using CLKINT buffer
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock networks. The A42MX36 device has four additional register control resources, called quadrant clock networks (Figure 1-8). Each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable.
CLKINB CLKINA
CLKMOD
S0 S1
Internal Signal CLKO(17)
Clock Drivers
CLKO(16) CLKO(15)
CLKO(2) CLKO(1)
Clock Tracks
Figure 1-7 * Clock Networks of 42MX Devices
QCLKA Quad Clock Modul QCLK1 QCLK3 Quad Clock Modul QCLKC QCLKD *QCLK3IN S0 S1 S1 S0
QCLKB *QCLK1IN
Quad Clock Modul *QCLK2IN S0 S1
QCLK2
QCLK4
Quad Clock Modul *QCLK4IN S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals. Figure 1-8 * Quadrant Clock Network of A42MX36 Devices
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40MX and 42MX Automotive FPGA Families
I/O Modules
The I/O modules provide the interface between the device pins and the logic array. Figure 1-9 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module. (Refer to the Antifuse Macro Library Guide for more information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be configured for input, output, or bidirectional operation. 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable control (Figure 1-9). The I/O module can be used to latch input or output data, or both, providing fast setup time. In addition, the Actel Designer software tools can build a Dtype flip-flop using a C-module combined with an I/O module to register input and output signals. Refer to the Antifuse Macro Library Guide for more details. Actel's Designer software development tools provide a design library of I/O macro functions that can implement all I/O configurations supported by the MX FPGAs.
EN
there is the Security Fuse which, when programmed, both disables the probing circuitry and prohibits further programming of the device. Look for this symbol to ensure your valuable IP is secure.
TM
ue
Figure 1-10 * Fuselock
For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note.
Programming
Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC. Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. After being programmed, each fuse is verified to insure that it has been programmed correctly. Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses have been programmed. Not only does it test fuses (both programmed and nonprogrammed), Silicon Sculptor II also allows self-test to verify its own hardware extensively. The procedure for programming an MX device using Silicon Sculptor II is as follows: 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via In-House Programming from the factory. For more details on programming MX devices, please refer to the Programming Antifuse Devices and the Silicon Sculptor II user's guides.
Q From Array
D PAD
G/CLK* To Array Q D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module) Figure 1-9 * 42MX I/O Module
Other Architectural Features
User Security
The Actel FuseLock provides robust security against design theft. Special security fuses are hidden in the fabric of the device and prevent unauthorized users from accessing the programming and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the device, making Actel antifuse FPGAs immune to both invasive and noninvasive attacks. Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse. In 42MX devices,
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40MX and 42MX Automotive FPGA Families
Power Supply
Automotive MX devices are designed to operate in 5.0V environments. Table 1-1 describes the voltage settings of automotive MX devices.
Table 1-1 * Voltage Support of Automotive-Grade MX Devices Device 40MX 42MX VCC 5.0V - VCCA - 5.0V VCCI - 5.0V Maximum Input Tolerance 5.25V 5.25V Nominal Output Voltage 5.0V 5.0V
Power-Up/Down
When powering up MX devices, VCCA must be greater than or equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during power-up, either the input protection junction on the I/Os will be forwardbiased or the I/Os will be at logical High, and ICC rises to high levels. During power-down, VCCA must be smaller than or equal to VCCI.
Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE pin is held HIGH. Figure 1-11 on page 1-7 illustrates the interconnection between Silicon Explorer II and 40MX devices, while Figure 1-12 on page 1-7 illustrates the interconnection between Silicon Explorer II and 42MX devices To allow for probing capabilities, the security fuses must not be programmed. (Refer to "User Security" section on page 1-5 for the security fuses of 40MX and 42MX devices). Table 1-2 on page 1-7 summarizes the possible device configurations for probing. PRA and PRB pins are dual-purpose pins. When the "Reserve Probe Pin" is checked in the Designer software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are required as user I/Os to achieve successful layout and "Reserve Probe Pin" is checked, the layout tool will override the option and place user I/Os on PRA and PRB pins.
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides builtin access to every node in a design, via the use of Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer software, allow users to examine any of the internal nodes of the device while it is operating in a prototyping or a production system. The user can probe an MX device without changing the placement and routing of the design and without using any additional resources. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle and providing a true representation of the device under actual functional situations. Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard serial port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds.
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40MX and 42MX Automotive FPGA Families
16 Logic Analyzer Channels
Serial Connection to Windows PC
40MX Silicon Explorer II MODE SDI DCLK SDO PRA
PRB
Figure 1-11 * Silicon Explorer II Setup with 40MX
16 Logic Analyzer Channels
Serial Connection to Windows PC
42MX Silicon Explorer II MODE SDI DCLK SDO PRA
PRB
Figure 1-12 * Silicon Explorer II Setup with 42MX Table 1-2 * Device Configuration Options for Probe Capability Security Fuse(s) Programmed No No Yes Notes: 1. Avoid using SDI, SDO, DCLK, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin Descriptions" section on page 1-45 for information on unused I/O pins. MODE LOW HIGH - PRA, PRB1 User I/Os2 Probe Circuit Outputs Probe Circuit Secured SDI, SDO, DCLK1 User I/Os2 Probe Circuit Inputs Probe Circuit Secured
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40MX and 42MX Automotive FPGA Families
Design Consideration
It is recommended to use a series 70 termination resistor on every probe connector (SDI, SDO, MODE, DCLK, PRA and PRB). The 70 series termination is used to prevent data transmission corruption during probing and reading back the checksum.
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. Automotive-grade 42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
Automotive-grade 42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers and instruction register (Figure 1-13). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/ PRELOAD and BYPASS) and some optional instructions. Table 1-3 on page 1-9 describes the ports that control JTAG testing, while Table 1-4 on page 1-9 describes the test instructions supported by these MX devices. Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input), TDI and TDO (test data input and output), and TMS (test mode selector).
Boundary Scan Register Bypass Register Control Logic JTAG TMS TCK JTAG TDI Instruction Register TAP Controller Instruction Decode
Output MUX
TDO
Figure 1-13 * 42MX IEEE 1149.1 Boundary Scan Circuitry
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40MX and 42MX Automotive FPGA Families
Table 1-3 * Test Access Port Descriptions Port TMS (Test Select) Description Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK)
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency for TCK is 20 MHz TDI (Test Data Input) TDO (Test Output) Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock
Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high impedance) when data scanning is not in progress
Table 1-4 * Supported BST Public Instructions Instruction EXTEST IR Code [2:0] 000 Instruction Type Mandatory Description Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins Allows a snapshot of the signals at the device pins to be captured and examined during operation Tristates all I/Os to allow external signals to drive pins. Please refer to the IEEE Standard 1149.1 specification for details Allows state of signals driven from component pins to be determined from the Boundary-Scan Register. Please refer to the IEEE Standard 1149.1 specification for details Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the test chain
SAMPLE/PRELOAD HIGH Z CLAMP
001 101 110
Mandatory Optional Optional
BYPASS
111
Mandatory
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JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools and then Device Selection. This brings up the Device Selection dialog box as shown in Figure 1-14. The JTAG test logic circuit can be enabled by clicking the "Reserve JTAG Pins" check box. Table 1-5 explains the pins' behavior in either mode.
Figure 1-14 * Device Selection Wizard Table 1-5 * Boundary Scan Pin Configuration and Functionality Reserve JTAG TCK TDI, TMS TDO Checked BST input; must be terminated to logical HIGH or LOW to avoid floating BST input; may float or be tied to HIGH. TDI may be tied to TDO of another device BST output; may float or be connected to TDI of another device Unchecked User I/O User I/O User I/O
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets the boundary-scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five TCK cycles.
Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be documented. The BSDL file provides the standard format to describe the JTAG components that can be used by automatic test equipment software. The file includes the instructions that are supported, instruction-bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files, please refer to Actel BSDL Files Format Description application note. Actel BSDL files are grouped into two categories-- generic and device-specific. The generic files assign all user I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs, or inouts. Generic files for MX devices are available on Actel's website at http://www.actel.com/techdocs/models/bsdl.html.
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Development Tool Support
The automotive-grade MX family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify(R) for Actel from Synplicity(R), ViewDraw for Actel from Mentor Graphics, ModelSimTM HDL Simulator from Mentor Graphics(R), WaveFormer LiteTM from SynaptiCADTM, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel's website) diagram for more information. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
Related Documents
Application Notes
Actel BSDL Files Format Description www.actel.com/documents/BSDLformat_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf Actel's Implementation of Security in Actel Antifuse FPGAs www.actel.com/documents/Antifuse_Security_AN.pdf
User's Guides and Manuals
Antifuse Macro Library Guide www.actel.com/documents/libguide_UG.pdf Silicon Sculptor II www.actel.com/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE Flow Diagram www.actel.com/products/tools/libero/flow.html
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5.0V Operating Conditions
Absolute Maximum Ratings*
Free Air Temperature Range
Symbol Parameter Limits -0.5 to +6.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 Units V V V C
Recommended Operating Conditions
Parameter Temperature Range VCCI VCCA VCC Notes: 1. Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing options available. 2. Ambient temperature (TA)
2
Automotive1 -40 to +125 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25
Units C V V V
VCC/VCCA/VCCI DC Supply Voltage VI VO TSTG Input Voltage Output Voltage Storage Temperature
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.
Electrical Specifications
Automotive Symbol VOH1 VOL1 VIL VIH IIL, IIH IOZ tR, tF CIO ICC2 IIO Notes: 1. Only one output tested at a time. VCC/VCCI = min. 2. All outputs unloaded. All inputs = VCC/VCCI or GND. Parameter Output High Voltage Output Low Voltage Input Low Voltage Input High Voltage Input Leakage Current Tristate Output Leakage Current Input Transition Time I/O Capacitance Standby Current I/O source sink current 2.1 -20 -20 20 20 250 10 35 Conditions (IOH = -4 mA) (IOL = 4 mA) Min. 3.1 0.4 0.6 Max. Units V V V V A A ns pF mA
Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
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Power Dissipation
General Power Equation
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI - VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active.
Active Power Component
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent and a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. The power dissipated by a CMOS circuit can be expressed by the equation: Power (W) = CEQ * VCCA2 * F
EQ 1-1
where:
CEQ = = =
Equivalent capacitance picofarads (pF) Power supply in volts (V)
expressed
in
VCCA
Static Power Component
Actel FPGAs have small static power components that result in power dissipation lower than PALs or CPLDs. By integrating multiple PALs/CPLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. The static power dissipation by TTL loads depends on the number of outputs driving HIGH or LOW, and on the DC load current. Again, this number is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving LOW, and 140 mW with all outputs driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.
F
Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown on the following page.
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CEQ Values for Actel MX FPGAs
Modules (CEQM)
Input Buffers (CEQI) Output Buffers (CEQO) 3.5 6.9 18.2 1.4
Fixed Capacitance Values for MX FPGAs (pF)
Device Type A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 r1 routed_Clk1 41.4 68.6 118 165 185 220 r2 routed_Clk2 N/A N/A 118 165 185 220
Routed Array Clock Buffer Loads (CEQCR)
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. The equation below shows a piece-wise linear summation over all components. Power = VCCA2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
EQ 1-2
Determining Average Switching Frequency
To determine the switching frequency for a design, the data input values to the circuit must be clearly understood. The following guidelines represent worstcase scenarios; these can be used to generally predict the upper limits of power dissipation.
Logic Modules (m) = 80% of Combinatorial Modules # of Inputs/4 # of Outputs/4 40% of Sequential Modules 40% of Sequential Modules 35 pF F/10 F/5 F/10 F F/2
where:
m n p q1 q2 r1 r2 CEQM CEQI CEQO = Number of logic modules switching at frequency fm = = = Number of input buffers switching at frequency fn Number of output buffers switching at frequency fp Number of clock loads on the first routed array clock
= Number of clock loads on the second routed array clock = = Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock
Inputs Switching (n) Outputs Switching (p) First Routed Array Clock Loads (q1)
= = =
= Equivalent capacitance of logic modules in pF = Equivalent capacitance of input buffers in pF = Equivalent capacitance of output buffers in pF Equivalent capacitance of routed array clock in pF Output load capacitance in p
Second Routed Array Clock Loads = (q2) Load Capacitance (CL) =
CEQCR = CL fm fn fp fq1 fq2 =
Average Logic Module Switching = Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) = =
= Average logic module switching rate in MHz = = = = Average input buffer switching rate in MHz Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz
Average First Routed Array Clock = Rate (fq1) Average Second Routed Array Clock = Rate (fq2)
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Junction Temperature
The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. EQ 1-3 can be used to calculate junction temperature. Junction Temperature = T + Ta (1)
EQ 1-3
T = ja * P P = Power ja = Junction to ambient of package. ja numbers are located in the "Package Thermal Characteristics" section.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at automotive temperature is as follows:
Where: Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient
Max. junction temp. (C) - Max. automotive temp. 150C - 125C ---------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 0.95W ja (C/W) 26.2C/W
Table 1-6 * Package Thermal Characteristics
ja
Plastic Packages Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Pin Count 100 160 208 240 68 84 176 80 100
jc
12.0 10.0 8.0 8.5 13.0 12.0 11.0 12.0 10.0
Still Air 27.8 26.2 26.1 25.6 25.0 22.5 24.7 38.2 35.3
1.0 m/s 200 ft./min. 23.4 22.8 22.5 22.3 21.0 18.9 19.9 31.9 29.4
2.5 m/s 500 ft./min. 21.2 21.1 20.8 20.8 19.4 17.6 18.0 29.4 27.1
Units C/W C/W C/W C/W C/W C/W C/W C/W C/W
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Timing Information
Input Delay I/O Module t INYL = 1.2 ns Internal Delays Predicted Routing Delays Output Delay I/O Module tIRD2 = 4.6 ns Logic Module t DLH = 5.9 ns t IRD1 = 3.7 ns t IRD4 = 6.5 ns t IRD8 = 10.2 ns t PD = 2.2 ns t CO = 2.2 ns t RD1 = 2.3 ns t RD2 = 3.2 ns t RD4 = 5.1 ns t RD8 = 8.8 ns tENHZ = 14.1 ns
Array Clock
tCKH = 8.1 ns F MAX = 116 MHz
FO = 128
Note: * Values are shown for 40MX at worst-case 5.0V automotive conditions. Figure 1-15 * 40MX Timing Model*
Input Delays I/O Module t INYL = 1.3 ns tIRD1 = 3.4 ns
Internal Delays
Predicted Routing Delays
Output Delays I/O Module
Combinatorial Logic Module D G tINH = 0.0 ns tINSU = 0.4 ns tINGL = 2.1 ns Sequential Logic Module Combinatorial Logic included in t SUD t SUD = 0.4 ns t HD = 0.0 ns D Q t RD1 = 1.1 ns G Q t PD = 2.0 ns t RD1 = 1.1 ns t RD2 = 1.6 ns tRD4 = 2.2 ns t RD8 = 3.8 ns
t DLH = 4.0 ns
I/O Module t DLH= 4.0 ns
D
Q tENHZ = 8.2 ns
Array Clocks
t CO = 2.1 ns
tOUTH = 0.00 ns tOUTSU = 0.4 ns tGLH = 4.3 ns
t CKH = 4.0 ns FMAX = 192 MHz
FO = 32
t LCO = 8.6 ns (light loads, pad-to-pad)
Notes: *Values are shown for A42MX09 at worst-case 5.0V automotive conditions. Input module predicted routing delay Figure 1-16 * 42MX Timing Model*
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Input Delays I/O Module tINPY = 1.7 ns t = 3.3 ns IRD1
Internal Delays
Predicted Routing Delays
Output Delays I/O Module
Combinatorial Module D G tINH = 0.0 ns tINSU = 0.8 ns tINGO = 2.4 ns Decode Module tPDD = 2.7 ns Q tPD = 2.3 ns tRD1 = 1.6 ns tRD2 = 2.2 ns tRD4 = 3.3 ns
t DLH= 4.3 ns
tRDD = 0.6 ns
Sequential Logic Module Combinatorial Logic included in t SUD tSUD = 0.6 ns tHD = 0.0 ns Quadrant Clocks tCKH = 4.5 ns tRD1= 1.6 ns D Q
I/O Module tDLH = 4.3 ns
D G
Q tENHZ = 8.8 ns
tCO = 2.2 ns
t LH = 0.0 ns tLSU = 0.8 ns tGHL = 5.0 ns
FMAX = 116 MHz
Notes: * Values are shown for A42MX36 at worst-case 5.0V automotive conditions. Load-dependent Figure 1-17 * A42MX36 Timing Model (Logic Functions using Quadrant Clocks)*
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40MX and 42MX Automotive FPGA Families
Input Delays I/O Module t INPY = 1.7 ns
t IRD1 = 3.3 ns
D G
Q
t INSU = 0.8 ns t INH = 0.0 ns t INGO = 2.4 ns
Predicted Routing Delays WD [7:0] WRAD [5:0] BLKEN WEN WCLK tADSU = 2.7 ns tADH = 0.0 ns t WENSU = 4.5 ns t BENS = 4.6 ns RD [7:0] RDAD [5:0] REN RCLK tADSU = 2.7 ns tADH = 0.0 ns tRENSU = 1.0 ns t RCO = 5.7 ns tRD1 = 1.6 ns
I/O Module tDLH = 4.3 ns
D G
Q
Array Clocks FMAX = 123 MHz
tGHL = 5.0 ns tLSU = 0.8 ns t LH = 0.0 ns
Note: *Values are shown for A42MX36 at worst-case 5.0V automotive conditions. Figure 1-18 * A42MX36 Timing Model (SRAM Functions)*
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Parameter Measurement
E D TRIBUFF o PAD T AC test loads (shown below)
In
50% 50% VOH 1.5V PAD 1.5V VOL tDHL tDLH
E
50% 50% VCCI 1.5V PAD 10% VOL tENZL tENLZ
E
50% 50% VOH PAD 90% 1.5V GND tENHZ tENZH
Figure 1-19 * Output Buffer Delays
Load 1 (Used to measure propagation delay) To the output under test 35 pF
Load 2 (Used to measure rising/falling edges) VCCI GND
To the output under test
R to VCCI for tPLZ /t PZL R to GND for t PHZ /t PZH R = 1 k
35 pF
Figure 1-20 * AC Test Loads
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40MX and 42MX Automotive FPGA Families
Sequential Timing Characteristics
Y
S, A or B 50% 50% S A B Y
PAD
INBUF
PAD Y GND
3V 1.5V 1.5V VCCI 50% t INYH
0V 50% tINYL
Y Y t PLH
50% PHL
50%
50% tPHL
50% tPLH
Figure 1-21 * Input Buffer Delays
Figure 1-22 * Module Delays
D E CLK
PRE CLR
Y
(Positive Edge-Triggered) t HD D1 t SUD G, CLK t SUENA t HENA E t CO Q t RS PRE, CLR t WASYN
Note: D represents all data functions involving A. B. and S for multiplexed flip-flops. Figure 1-23 * Flip-Flops and Latches
t WCLKA t WCLKI
tA
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D OBDLHS G
PAD
D tOUTSU G tOUTH
Figure 1-25 * Output Buffer Latches
DATA
PAD G
IBDL
CLK
PAD
DATA tINH G tINSU tH EXT CLK tSU EXT
Figure 1-24 * Input Buffer Latches
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Decode Module Timing
A B C D E F G
H
Y
A-G, H
50%
Y tPHL tPLH
Figure 1-26 * Decode Module Timing
Write Port WRAD [5:0] BLKEN WEN WCLK WD [7:0] RAM Array 3 2x8 or 64x4 (2 56 Bits) Read Port RDAD [5:0] LEW REN RCLK RD [7:0]
Figure 1-27 * SRAM Timing Characteristics
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Dual-Port SRAM Timing Waveforms
t RCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid t WENSU WEN t BENSU BLKEN
Note: Identical timing for falling edge clock. Figure 1-28 * 42MX SRAM Write Operation
t RCKHL
tADH
t WENH
tBENH
Valid
t CKHL RCLK
t RCKHL
tRENSU REN tADSU RDAD[5:0] Valid tDOH RD[7:0]
Note: Identical timing for falling edge clock. Figure 1-29 * 42MX SRAM Synchronous Read Operation
tRENH
tADH
tRCO New Data
Old Data
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(Read Address Controlled) t RDADV RDAD[5:0] ADDR1 t DOH RD[7:0] Data 1 ADDR2 t RPD Data 2
Figure 1-30 * 42MX SRAM Asynchronous Read Operation--Type 1
(Write Address Controlled) WEN
t WENSU
t WENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Old Data
New Data
Figure 1-31 * 42MX SRAM Asynchronous Read Operation--Type 2
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Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented antifuse offers a very low resistive/ capacitive interconnect. The antifuses, fabricated in 0.45 lithography, offer nominal levels of 100 resistance and 7.0 femtofarad (fF) capacitance per antifuse. MX fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects using only two antifuses.
Critical Nets and Typical Nets
Propagation delays in this datasheet apply to typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment in Actel's Designer software prior to placement and routing. Up to 6% of the nets in a design may be designated as critical.
Long Tracks
Some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing delays in the datasheet specifications section beginning on page 1-16.
Timing Derating
MX devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature and worst-case processing.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, and designdependent. The input and output buffer characteristics are common to all MX devices. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after place-and-route of the user's design is complete. Delay values may then be determined by using the Timer tool in the Designer software or by performing simulation with postlayout delays.
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Temperature and Voltage Derating Factors
Table 1-7 * 42MX Temperature and Voltage Derating Factors (Normalized to TJ = 125C, VCCA/VCCI = 4.75V) 42MX Voltage 4.75 5.00 5.25 Temperature -55C 0.66 0.64 0.62 -40C 0.67 0.65 0.64 0C 0.74 0.72 0.70 25C 0.78 0.75 0.73 70C 0.89 0.87 0.84 85C 0.91 0.89 0.86 125C 1.00 0.97 0.94
42MX Derating Factor (Normalized to TJ = 125C, VCCA /VCCI =4.75V)
1.10 1.00 Derating Factor 0.90 0.80 0.70 0.60 0.50 0.40 4.75 5.00 Voltage (V)
Note: This derating factor applies to all routing and propagation delays. Figure 1-32 * 42MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 125C, VCCA/VCCI = 4.75V)
-55C -40C 0C 25C 70C 85C 125C
5.25
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Table 1-8 * 40MX Temperature and Voltage Derating Factors (Normalized to TJ = 125C, VCC = 4.75V) 40MX Voltage 4.75 5.00 5.25 Temperature -55C -40C 0C 25C 70C 85C 125C
0.62 0.60 0.58
0.64 0.62 0.60
0.71 0.69 0.67
0.75 0.73 0.71
0.86 0.84 0.82
0.90 0.88 0.85
1.00 0.97 0.94
40MX Derating Factor (Normalized to T = 125C, VCC = 4.75V) J
1.10 1.00 Derating Factor 0.90 0.80 0.70 0.60 0.50 0.40 4.75 5.00 Voltage (V) 5.25
-55C -40C 0C 25C 70C 85C 125C
Note: This derating factor applies to all routing and propagation delays. Figure 1-33 * 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 125C, VCC 4.75V)
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Timing Characteristics
The timing numbers in the datasheet represent sample timing characteristics of the devices. Refer to the Timer tool in the Designer software for design-specific timing information.
Table 1-9 * A40MX02 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125C Std. Speed Parameter Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD3 tSUENA tHENA tWCLKA tWASYN tA fMAX tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this macro. 4. Delays based on 35 pF loading. Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
1 1
Description
Min.
Max. 2.2 4.7 2.2 2.2 2.2 2.3 3.2 4.2 5.1 8.8
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2
Logic Module Sequential Timing
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Flip-Flop (Latch) Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency Pad-to-Y HIGH Pad-to-Y LOW
1
5.4 0.0 5.4 0.0 5.8 5.8 8.7 116 1.3 1.2 3.7 4.6 5.6 6.5 10.2
MHz ns ns ns ns ns ns ns
Input Module Propagation Delays
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
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v3.1
40MX and 42MX Automotive FPGA Families
Table 1-9 * A40MX02 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125C (Continued) Std. Speed Parameter Global Clock Networks tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to HIGH Input High to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 TTL Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this macro. 4. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW 5.9 7.1 6.7 8.3 14.1 10.4 0.03 0.05 ns ns ns ns ns ns ns/pF ns/pF 8.3 8.7 120 116 3.9 4.2 3.9 4.2 0.7 0.9 8.1 8.1 8.6 8.6 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz Description Min. Max. Units
v3.1
1-29
40MX and 42MX Automotive FPGA Families
Table 1-10 * A40MX04 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125C Std. Speed Parameter Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1 2.4 3.4 4.3 5.2 9.0 ns ns ns ns ns
1
Description
Min.
Max.
Units
2.2 4.7 2.2 2.2 2.2
ns ns ns ns ns
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential tSUD tHD3 tSUENA tHENA tWCLKA tWASYN tA fMAX
Timing2 5.4 0.0 5.4 0.0 5.8 5.8 8.7 116 ns ns ns ns ns ns ns MHz
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Flip-Flop (Latch) Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency
Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y LOW Delays1 3.7 4.6 5.6 6.5 10.2 ns ns ns ns ns 1.3 1.2 ns ns
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this macro. 4. Delays based on 35 pF loading.
1 -3 0
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-10 * A40MX04 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125C Std. Speed Parameter Global Clock Network tCKH Input Low to HIGH FO = 16 FO = 128 tCKL Input High to LOW FO = 16 FO = 128 tPWH Minimum Pulse Width HIGH FO = 16 FO = 128 tPWL Minimum Pulse Width LOW FO = 16 FO = 128 tCKSW Maximum Skew FO = 16 FO = 128 tP Minimum Period FO = 16 FO = 128 fMAX Maximum Frequency
4
Description
Min.
Max.
Units
8.2 8.2 8.7 8.7 3.9 4.2 3.9 4.2 0.7 0.9 8.3 8.7 120 116
ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
FO = 16 FO = 128
TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes:
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW
5.9 7.1 6.7 8.3 14.1 10.4 0.03 0.05
ns ns ns ns ns ns ns/pF ns/pF
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this macro. 4. Delays based on 35 pF loading.
v3.1
1-31
40MX and 42MX Automotive FPGA Families
Table 1-11 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter Logic Module Propagation tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX tINYH tINYL tINGH tINGL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Delays1 2.0 2.1 2.0 2.4
2
Description
Min.
Max.
Units
Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
ns ns ns ns
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing3, 4
1.1 1.6 1.9 2.2 3.8
ns ns ns ns ns
Logic Module Sequential
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
0.4 0.0 0.6 0.0 4.8 6.3 4.8 0.0 0.4 0.0 0.4 174
ns ns ns ns ns ns ns ns ns ns ns MHz
Input Module Propagation Delays Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW 1.8 1.3 2.1 2.1 ns ns ns ns
1 -3 2
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-11 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2
Description
Min.
Max.
Units
3.4 3.8 4.2 4.6 6.2
ns ns ns ns ns
Global Clock Network Input Low to HIGH FO = 32 FO = 256 Input High to LOW FO = 32 FO = 256 Minimum Pulse Width HIGH FO = 32 FO = 256 Minimum Pulse Width LOW FO = 32 FO = 256 Maximum Skew FO = 32 FO = 256 Input Latch External Setup FO = 32 FO = 256 Input Latch External Hold FO = 32 FO = 256 Minimum Period FO = 32 FO = 256 Maximum Frequency Timing5 4.0 4.8 4.4 ns ns ns FO = 32 FO = 256 TTL Output Module tDLH tDHL tENZH Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 0.0 0.0 3.9 4.4 5.3 5.8 192 174 2.0 2.2 2.0 2.2 0.6 0.6 4.0 4.5 5.8 6.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH
v3.1
1-33
40MX and 42MX Automotive FPGA Families
Table 1-11 * A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 0.8 0.0 8.6 12.2 0.04 0.06 Description Min. Max. 4.8 8.2 8.9 4.3 4.3 Units ns ns ns ns ns ns ns ns ns ns/pF ns/pF
1 -3 4
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-12 * A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter Logic Module Propagation Delays1 tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX tINYH tINYL tINGH tINGL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2 1.3 1.7 2.1 2.6 4.3 ns ns ns ns ns 2.2 2.4 2.2 2.6 ns ns ns ns Description Min. Max. Units
Logic Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3,4 Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.6 0.0 1.1 0.0 5.6 7.4 11.3 0.0 0.8 0.0 0.8 139 ns ns ns ns ns ns ns ns ns ns ns MHz
Input Module Propagation Delays Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW 1.8 1.3 2.4 2.4 ns ns ns ns
v3.1
1-35
40MX and 42MX Automotive FPGA Families
Table 1-12 * A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.0 3.5 3.9 4.4 6.1 ns ns ns ns ns Description Min. Max. Units
Global Clock Network Input Low to HIGH FO = 32 FO = 384 Input High to LOW FO = 32 FO = 384 Minimum Pulse Width HIGH FO = 32 FO = 384 Minimum Pulse Width LOW FO = 32 FO = 384 Maximum Skew FO = 32 FO = 384 Input Latch External Setup FO = 32 FO = 384 Input Latch External Hold FO = 32 FO = 384 Minimum Period FO = 32 FO = 384 Maximum Frequency Timing5 4.2 4.9 4.5 ns ns ns FO = 32 FO = 384 TTL Output Module tDLH tDHL tENZH Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 0.0 0.0 4.6 5.3 6.5 7.2 153 139 5.3 6.1 5.3 6.1 0.6 0.6 4.4 4.8 6.3 7.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH
1 -3 6
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-12 * A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW Description Min. Max. 4.9 9.0 8.3 4.8 4.8 9.4 13.3 0.04 0.06 Units ns ns ns ns ns ns ns ns/pF ns/pF
v3.1
1-37
40MX and 42MX Automotive FPGA Families
Table 1-13 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter Logic Module Combinatorial Functions1 tPD tPDD Internal Array Module Delay Internal Decode Module Delay 2.0 2.4 ns ns Description Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.4 1.7 2.2 2.5 4.1 ns ns ns ns ns
Logic Module Sequential Timing3, 4 tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.7 0.0 5.5 7.4 0.6 0.0 2.4 2.2 2.0 ns ns ns ns ns ns ns ns ns
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.8 7.8 1.7 2.2 ns ns ns ns ns
1 -3 8
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-13 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.1 3.5 3.8 4.2 5.8 ns ns ns ns ns Description Min. Max. Units
Global Clock Network tCKH Input Low to HIGH FO = 32 FO = 486 tCKL Input High to LOW FO = 32 FO = 486 tPWH Minimum Pulse Width HIGH FO = 32 FO = 486 tPWL Minimum Pulse Width LOW FO = 32 FO = 486 tCKSW Maximum Skew FO = 32 FO = 486 tSUEXT Input Latch External Setup FO = 32 FO = 486 tHEXT Input Latch External Hold FO = 32 FO = 486 tP Minimum Period FO = 32 FO = 486 fMAX Maximum Frequency FO = 32 FO = 486 Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. 0.0 0.0 4.6 5.5 7.4 8.0 135 124 3.6 4.0 3.6 4.0 0.9 0.9 4.4 4.9 6.1 7.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
v3.1
1-39
40MX and 42MX Automotive FPGA Families
Table 1-13 * A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125C Std. Speed Parameter TTL Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 0.8 0.0 9.2 17.8 0.06 0.05 4.1 4.8 4.3 4.8 8.6 8.0 4.9 4.9 ns ns ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF Description Min. Max. Units
1 -4 0
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-14 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125C Std. Speed Parameter Logic Module Combinatorial Functions tPD tPDD
1
Description
Min.
Max.
Units
Internal Array Module Delay Internal Decode Module Delay
2
2.3 2.7
ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.6 2.2 2.7 3.3 5.5 0.6
ns ns ns ns ns ns
Decode-to-Output Routing Delay
3, 4
Logic Module Sequential Timing tCO tGO tSUD tHD tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 1.1 0.0 5.5 7.2 0.6 0.0
2.2 2.2
ns ns ns ns
2.6
ns ns ns ns ns
Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time 2.7 0.0 11.3 11.3 5.7 5.7 ns ns ns ns ns ns
v3.1
1-41
40MX and 42MX Automotive FPGA Families
Table 1-14 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125C (Continued) Std. Speed Parameter tRENSU tRENH tWENSU tWENH tBENS tBENH Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold Description Min. 1.0 5.7 4.5 0.0 4.6 0.0 Max. Units ns ns ns ns ns ns
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 14.7 2.7 0.0 1.0 5.7 4.5 0.0 2.0 13.6 ns ns ns ns ns ns ns ns ns
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.8 7.8 1.7 2.4 ns ns ns ns ns
Input Module Predicted Routing Delays2 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.3 3.8 4.4 5.0 7.2 ns ns ns ns ns
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v3.1
40MX and 42MX Automotive FPGA Families
Table 1-14 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125C (Continued) Std. Speed Parameter Global Clock Network tCKH Input Low to HIGH FO = 32 FO = 635 tCKL Input High to LOW FO = 32 FO = 635 tPWH Minimum Pulse Width HIGH FO = 32 FO = 635 tPWL Minimum Pulse Width LOW FO = 32 FO = 635 tCKSW Maximum Skew FO = 32 FO = 635 tSUEXT Input Latch External Setup FO = 32 FO = 635 tHEXT Input Latch External Hold FO = 32 FO = 635 tP Minimum Period FO = 32 FO = 635 fMAX Maximum Frequency FO = 32 FO = 635 TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.
1
Description
Min.
Max.
Units
4.5 5.0 6.3 8.1 2.9 3.3 2.9 3.3 1.1 1.1 0.0 0.0 4.8 5.5 8.6 9.4 116 107
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH
4.3 5.0 4.4 4.9 8.8 8.3 5.0
ns ns ns ns ns ns ns
v3.1
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40MX and 42MX Automotive FPGA Families
Table 1-14 * A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125C (Continued) Std. Speed Parameter tGHL tLSU tLH tLCO tACO dTLH dTHL Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer tool. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/ hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 32 I/O Array Clock-to-Out (Pad-to-Pad), 32 I/O Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW 0.8 0.0 9.5 13.0 0.11 0.11 Description Min. Max. 5.0 Units ns ns ns ns ns ns/pF ns/pF
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v3.1
40MX and 42MX Automotive FPGA Families
Pin Descriptions
CLK/A/B, I/O Global Clock PRA/B, I/O Probe
Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
DCLK, I/O Diagnostic Clock
TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
GND Ground
The Probe pin is used to output data from any userdefined design node within the device. Each diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a userdefined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. The Probe pin is accessible when the MODE pin is High. This pin functions as an I/O when the MODE pin is Low.
QCLKA,B,C,D, I/O Quadrant Clock
Input LOW supply voltage.
I/O Input/Output
Input, output, tristate, or bidirectional buffer. Input and output levels are compatible with standard TTL specifications. Unused I/O pins are configured by the Designer software as shown in Table 1-15.
Table 1-15 * Configuration of Unused I/Os Device A40MX02, A40MX04 A42MX09, A42MX16 A42MX24, A42MX36 Configuration Pulled LOW Pulled LOW Tristated
Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can function as general-purpose I/Os.
SDI, I/O Serial Data Input
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is High. This pin functions as an I/O when the MODE pin is Low.
SDO, TDO, I/O Serial Data Output
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is High. This pin functions as an I/O when the MODE pin is Low. SDO is available for 42MX devices only. When Silicon Explorer II is being used, SDO will act as an output while the "checksum" is run. It will return to user I/O when "checksum" is complete.
TCK, I/O Test Clock
In all cases, it is recommended to tie all unused I/O pins to LOW on the board. This applies to all dual-purpose pins when configured as I/Os as well.
MODE Mode
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). To provide verification capability, the MODE pin should be held HIGH. To facilitate this, the MODE pin should be tied to GND through a 10k resistor so that the MODE pin can be pulled HIGH when required.
NC No Connection
Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer software. BST pins are only available in the A42MX24 and A42MX36 devices.
TDI, I/O Test Data In
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer software. BST pins are only available in the A42MX24 and A42MX36 devices.
v3.1
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40MX and 42MX Automotive FPGA Families TDO, I/O Test Data Out VCC Supply Voltage
Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer software. BST pins are only available in the A42MX24 and A42MX36 devices.
TMS, I/O Test Mode Select
Supply voltage for 40MX devices.
VCCA Supply Voltage
Supply voltage for array in 42MX devices.
VCCI Supply Voltage
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI and TDO pins are boundary-scan pins. Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached five TCK cycles after the TMS pin is set High. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG specification recommends a 10k pull-up resistor on the pin. BST pins are only available in A42MX24 and A42MX36 devices.
Supply voltage for I/Os in 42MX devices.
WD, I/O Wide Decode Output
When a wide decode module is used in a an A42MX24 or A42MX36 device, this pin can be used as a dedicated output from the wide decode module. This direct connection eliminates additional interconnect delays associated with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type to the output of the wide decode macro and place this output on one of the reserved WD pins. When a wide decode module is not used, this pin functions as a regular I/O pin.
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v3.1
40MX and 42MX Automotive FPGA Families
Package Pin Assignments
68-Pin PLCC
1 68
68-Pin PLCC
Figure 2-1 * 68-Pin PLCC
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-1
40MX and 42MX Automotive FPGA Families
68-Pin PLCC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 A40MX02 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC I/O I/O I/O VCCy I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O Pin Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
68-Pin PLCC A40MX02 Function I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O
2 -2
v3.1
40MX and 42MX Automotive FPGA Families
84-Pin PLCC
1 84
84-Pin PLCC
Figure 2-2 * 84-Pin PLCC
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-3
40MX and 42MX Automotive FPGA Families
84-Pin PLCC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 A40MX04 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O A42MX09 Function I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O DCLK, I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
84-Pin PLCC A40MX04 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLK, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O A42MX09 Function VCCA I/O I/O I/O I/O I/O GND I/O I/O SDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA
2 -4
v3.1
40MX and 42MX Automotive FPGA Families
100-Pin PQFP
100-Pin PQFP
100 1
Figure 2-3 * 100-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-5
40MX and 42MX Automotive FPGA Families
100-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A40MX02 Function NC NC NC NC NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC NC I/O I/O A40MX04 Function NC NC NC NC NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O A42MX09 Function I/O DCLK, I/O I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-Pin PQFP A40MX02 Function GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O NC NC NC NC NC NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O A40MX04 Function GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O NC NC NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O A42MX09 Function I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCCA VCCI VCCA I/O I/O I/O
2 -6
v3.1
40MX and 42MX Automotive FPGA Families
100-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A40MX02 Function I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC I/O I/O I/O GND GND I/O I/O CLK, I/O I/O MODE VCC VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O A40MX04 Function I/O I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLK, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O A42MX09 Function I/O GND I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O
v3.1
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40MX and 42MX Automotive FPGA Families
160-Pin PQFP
160 1
160-Pin PQFP
Figure 2-4 * Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
2 -8
v3.1
40MX and 42MX Automotive FPGA Families
160-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A42MX09 Function I/O DCLK, I/O NC I/O I/O NC I/O I/O I/O NC GND NC I/O I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O NC I/O I/O I/O NC I/O GND NC I/O I/O I/O NC I/O I/O SDI, I/O I/O GND A42MX24 Function I/O DCLK, I/O I/O WD, I/O WD, I/O VCCI I/O I/O I/O I/O GND I/O WD, I/O WD, I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O WD, I/O WD, I/O I/O I/O I/O WD, I/O GND WD, I/O I/O I/O I/O VCCI WD, I/O WD, I/O SDI, I/O I/O GND Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
160-Pin PQFP A42MX09 Function I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O NC I/O NC I/O I/O VCCA VCCI GND VCCA GND I/O I/O GND I/O I/O I/O I/O GND NC I/O I/O I/O I/O NC I/O NC I/O NC GND A42MX24 Function I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA GND TCK, I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
v3.1
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40MX and 42MX Automotive FPGA Families
160-Pin PQFP Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 A42MX09 Function I/O SDO, I/O I/O I/O I/O NC I/O I/O GND NC I/O I/O I/O I/O I/O I/O I/O VCCA GND NC I/O I/O NC I/O I/O I/O I/O I/O GND NC I/O I/O I/O NC I/O NC I/O I/O I/O GND A42MX24 Function I/O SDO, TDO, I/O WD, I/O WD, I/O I/O VCCI I/O WD, I/O GND I/O I/O I/O I/O I/O I/O WD, I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O GND I/O WD, I/O WD, I/O I/O VCCI WD, I/O WD, I/O I/O TDI, I/O TMS, I/O GND Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
160-Pin PQFP A42MX09 Function I/O I/O I/O NC GND I/O I/O I/O NC GND I/O I/O I/O I/O NC I/O I/O NC VCCI GND NC I/O I/O I/O GND NC I/O I/O I/O NC NC NC NC NC GND I/O I/O I/O MODE GND A42MX24 Function I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O MODE GND
2 -1 0
v3.1
40MX and 42MX Automotive FPGA Families
80-Pin VQFP
80 1
80-Pin VQFP
Figure 2-5 * 80-Pin VQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-11
40MX and 42MX Automotive FPGA Families
80-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A40MX02 Function I/O NC NC NC I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC A40MX04 Function I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
80-Pin VQFP A40MX02 Function I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O A40MX04 Function I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O
2 -1 2
v3.1
40MX and 42MX Automotive FPGA Families
208-Pin PQFP
1
208
208-Pin PQFP
Figure 2-6 * 208-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-13
40MX and 42MX Automotive FPGA Families
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX16 Function GND NC MODE I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O NC VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O A42MX24 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O A42MX36 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
208-Pin PQFP A42MX16 Function I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O NC NC GND GND I/O I/O I/O I/O I/O I/O VCCI NC NC I/O I/O I/O I/O NC NC I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O I/O QCLKA, I/O WD, I/O WD, I/O I/O I/O WD, I/O
2 -1 4
v3.1
40MX and 42MX Automotive FPGA Families
208-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX16 Function I/O I/O I/O I/O I/O I/O I/O GND VCCA NC I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O NC NC NC VCCI I/O I/O I/O I/O SDO, I/O I/O GND A42MX24 Function WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O A42MX36 Function WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O QCLKB, I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
208-Pin PQFP A42MX16 Function NC I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O A42MX24 Function VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O A42MX36 Function VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O
SDO, TDO, I/O SDO, TDO, I/O I/O GND I/O GND
v3.1
2-15
40MX and 42MX Automotive FPGA Families
208-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 A42MX16 Function NC I/O I/O I/O I/O NC NC NC NC GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O I/O I/O VCCI NC NC I/O I/O I/O I/O NC I/O I/O I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O QCLKD, I/O I/O I/O I/O I/O Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
208-Pin PQFP A42MX16 Function I/O I/O PRA, I/O I/O CLKA, I/O NC NC VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O NC NC NC I/O NC I/O I/O I/O NC VCCI I/O I/O I/O I/O DCLK, I/O I/O A42MX24 Function WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O A42MX36 Function WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O QCLKC, I/O I/O I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O
2 -1 6
v3.1
40MX and 42MX Automotive FPGA Families
240-Pin PQFP
* * *
240 1
* * *
240-Pin PQFP
* * *
Figure 2-7 * 240-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
* * *
v3.1
2-17
40MX and 42MX Automotive FPGA Families
240-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A42MX36 Function I/O DCLK, I/O I/O I/O I/O WD, I/O WD, I/O VCCI I/O I/O I/O I/O I/O I/O QCLKC, I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O PRB, I/O I/O CLKB, I/O I/O GND VCCA VCCI I/O CLKA, I/O I/O PRA, I/O I/O I/O WD, I/O WD, I/O I/O I/O
240-Pin PQFP Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 A42MX36 Function I/O I/O I/O I/O QCLKD, I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O SDI, I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O
240-Pin PQFP Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 A42MX36 Function I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI VCCA GND TCK, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND
2 -1 8
v3.1
40MX and 42MX Automotive FPGA Families
240-Pin PQFP Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 A42MX36 Function GND I/O SDO, TDO, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O I/O WD, I/O WD, I/O I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O VCCI VCCA GND I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O
240-Pin PQFP Pin Number 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 A42MX36 Function I/O I/O WD, I/O WD, I/O I/O QCLKA, I/O I/O I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O I/O TDI, I/O TMS, I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O
240-Pin PQFP Pin Number 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 A42MX36 Function I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND MODE VCCA GND
v3.1
2-19
40MX and 42MX Automotive FPGA Families
100-Pin VQFP
100 1
100-Pin VQFP
Figure 2-8 * 100-Pin VQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
2 -2 0
v3.1
40MX and 42MX Automotive FPGA Families
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX09 Function I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O A42MX16 Function I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-Pin VQFP A42MX09 Function I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCCA VCCI VCCA I/O I/O I/O I/O GND A42MX16 Function I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCCA VCCI VCCA I/O I/O I/O I/O GND
v3.1
2-21
40MX and 42MX Automotive FPGA Families
100-Pin VQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A42MX09 Function I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O DCLK, I/O A42MX16 Function I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O DCLK, I/O
2 -2 2
v3.1
40MX and 42MX Automotive FPGA Families
176-Pin TQFP
176 1
176-Pin TQFP
Figure 2-9 * 176-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-23
40MX and 42MX Automotive FPGA Families
176-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A42MX09 Function GND MODE I/O I/O I/O I/O I/O NC I/O NC NC I/O NC I/O I/O I/O I/O GND NC NC I/O NC GND NC VCCA NC NC VCCI NC I/O I/O I/O NC I/O I/O A42MX16 Function GND MODE I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O A42MX24 Function GND MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
176-Pin TQFP A42MX09 Function I/O NC NC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC I/O NC NC I/O NC I/O I/O I/O NC I/O I/O NC I/O NC GND VCCA I/O I/O A42MX16 Function I/O I/O NC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND TMS, I/O TDI, I/O I/O WD, I/O WD, I/O I/O VCCI I/O I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O I/O I/O GND VCCA WD, I/O WD, I/O
2 -2 4
v3.1
40MX and 42MX Automotive FPGA Families
176-Pin TQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A42MX09 Function I/O I/O I/O NC I/O I/O NC NC I/O NC I/O NC I/O I/O I/O NC SDO, I/O I/O GND I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O NC I/O NC I/O I/O A42MX16 Function I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCI I/O I/O I/O I/O SDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O A42MX24 Function I/O I/O I/O I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI I/O WD, I/O WD, I/O I/O SDO, TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
176-Pin TQFP A42MX09 Function GND NC NC LP VCCA GND VCCI VCCA NC NC NC I/O I/O I/O I/O NC I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O NC I/O I/O I/O NC A42MX16 Function GND I/O I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O I/O I/O VCCI A42MX24 Function GND I/O TCK, I/O LP VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O WD, I/O WD, I/O I/O VCCI
v3.1
2-25
40MX and 42MX Automotive FPGA Families
176-Pin TQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 A42MX09 Function I/O I/O NC NC NC I/O NC I/O I/O I/O NC PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O A42MX16 Function I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O A42MX24 Function I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O I/O WD, I/O WD, I/O PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O Pin Number 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
176-Pin TQFP A42MX09 Function I/O PRB, I/O NC I/O I/O I/O NC NC I/O NC I/O NC I/O I/O NC I/O DCLK, I/O I/O A42MX16 Function I/O PRB, I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCI I/O I/O I/O I/O DCLK, I/O I/O A42MX24 Function I/O PRB, I/O WD, I/O WD, I/O I/O I/O WD, I/O WD, I/O I/O I/O I/O VCCI WD, I/O WD, I/O I/O I/O DCLK, I/O I/O
2 -2 6
v3.1
40MX and 42MX Automotive FPGA Families
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version v3.0 April 2004 v2.0 Changes in Current Version v3.1 A note was added to the "Ordering Information". Note 1 was added to "Recommended Operating Conditions". The "Speed Grade and Temperature Grade Matrix" table is new. The "Clock Networks" section was updated. The "I/O Modules" section was updated. The "Other Architectural Features" section is new The "Development Tool Support" section was updated. The "Electrical Specifications" table was updated. The "Junction Temperature" section was updated. Table 1-6 was updated. Figure 1-15 and Figure 1-16 were updated. Figure 1-17 was updated. Figure 1-18 was updated. The "Critical Nets and Typical Nets" section was updated. The "Timing Derating" section is new. Table 1-7 and Figure 1-32 were updated. Table 1-8 and Figure 1-33 were updated. All timing numbers contained in Table 1-9 through Table 1-14 were updated. The "Pin Descriptions" section was updated. Page ii 1-12 page 1-ii page 1-4 page 1-5 page 1-5 page 1-11 page 1-12 page 1-15 page 1-15 page 1-16 page 1-17 page 1-18 page 1-25 page 1-25 page 1-26 page 1-27 page 1-28 to page 1-41 page 1-45
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
Unmarked (production)
This datasheet version contains information that is considered to be final.
v3.1 3-1
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